Architecture Specification

This page describes the specification of an architecture template using XML. Basically, in DAL, an architecture is represented as a set of processors that are connected by a hierarchically organized set of networks.

Processors

The type of each processing unit needs to be specified, together with its capabilities. For instance, the following processor is is capable of handling POSIX code and OpenCL kernels.

<processor name="core_0" type="RISC" id="0">
	<port name="port1"/>
	<capability name="posix" identifier="0"/>
	<capability name="opencl" identifier="CPU_4098_Intel(R)Core(TM)i7-2600KCPU@3.40GHz_DEV1"/>
</processor>

The following processor describes a GPU that is only capable of executing OpenCL kernels. Note that DAL is able to generate OpenCL kernels automatically from an ordinary process specification.

<processor name="gpu" type="GPU" id="1">
	<port name="port1"/>
	<capability name="opencl" identifier="GPU_4098_Capeverde_DEV1"/>
</processor>

1. The processor tag specifies a processing element with a given name and some type. The type can be one of the following: RISC, DSP or GPU and is used to check the accuracy of a defined mapping later. The id attribute is used to internally assign a core identifier.
2. The port tag adds an interface with name to the processor which allows communication.
3. The capability tag specifies whether the processor is capable of handling posix code or opencl kernels according to the name attribute. The identifier attribute is for posix capabilities a simple number, but for opencl it is more complex and explained below.

The identifier tag is only required if the OpenCL back-end is used and has the following structure: <type>_<id>_<name>_DEV<number>

1. <type>: is the device type which can be either CPU, GPU or ACC (accelerator).
2. <id>: is the device identifier.
3. <name>: is the device name without any spaces or underscores.
4. <number>: is the number of the device, if there is more than one with the same name.

For an AMD Radeon HD 7750 GPU (Codename "Cape Verde"), the identifier would read as: GPU_4098_Capeverde_DEV1.

Tile

All processors belonging to the same tile share typically the global memory. In fact, a tile is simply defined as a set of ports that are used to connect the processors. Note that, for simplicity, the actual memory is not specified.

<shared name="localhost">
	<port name="port1"/>
	<port name="port2"/>
</shared>

1. The shared tag specifies a tile with a given name.
2. The port tag adds an interface with name to the tile which allows communication.

Networks

The noc refer to a network and has one attribute name of type string that is the name of the network. The element noc might contain a list of ports to specify its connection with local tiles.

<noc name="network_1" >
  <port name="port_1"/>
  <port name="port_2"/>
  <port name="port_3"/>
<noc>

Connections

The actual connections between the processors and the tiles and between the tiles and the networks are similar to the connections of the process network:

<link name="link_1">
	<end_point_1 name="gpu">
		<port name="port1"/>
	</end_point_1>
	<end_point_2 name="localhost">
		<port name="port2"/>
	</end_point_2>
</link>

1. The link tag specifies a link with a given name between a processor and a shared memory.
2. The end_point_1 and end_point_2 tags select the processor / shared memory with name as one of the end points of the connection.
3. The port tag selects the port with name from the processor / shared memory which needs to be connected.

Example

The following example shows an architecture with a quad-core processor and an additional GPU.

<architecture name="Quad-core platform with GPU">
	<processor name="core_0" type="RISC" id="0">
		<port name="port1"/>
		<capability name="posix" identifier="0"/>
		<capability name="opencl" identifier="CPU_4098_Intel(R)Core(TM)i7-2600KCPU@3.40GHz_DEV1"/>
	</processor>
	<processor name="core_1" type="RISC" id="1">
		<port name="port1"/>
		<capability name="posix" identifier="1"/>
		<capability name="opencl" identifier="CPU_4098_Intel(R)Core(TM)i7-2600KCPU@3.40GHz_DEV1"/>
	</processor>
	<processor name="core_2" type="RISC" id="2">
		<port name="port1"/>
		<capability name="posix" identifier="2"/>
		<capability name="opencl" identifier="CPU_4098_Intel(R)Core(TM)i7-2600KCPU@3.40GHz_DEV1"/>
	</processor>
	<processor name="core_3" type="RISC" id="3" substitute="1">
		<port name="port1"/>
		<capability name="posix" identifier="3"/>
		<capability name="opencl" identifier="CPU_4098_Intel(R)Core(TM)i7-2600KCPU@3.40GHz_DEV1"/>
	</processor>
 
	<processor name="gpu" type="GPU" id="4">
		<port name="port1"/>
		<capability name="opencl" identifier="GPU_4098_Capeverde_DEV1"/>
	</processor>
 
	<shared name="localhost">
		<port name="port1"/>
		<port name="port2"/>
		<port name="port3"/>
		<port name="port4"/>
		<port name="port5"/>
	</shared>
 
	<link name="link_1">
		<end_point_1 name="core_0">
			<port name="port1"/>
		</end_point_1>
		<end_point_2 name="localhost">
			<port name="port1"/>
		</end_point_2>
	</link>
	<link name="link_2">
		<end_point_1 name="core_1">
			<port name="port1"/>
		</end_point_1>
		<end_point_2 name="localhost">
			<port name="port2"/>
		</end_point_2>
	</link>
	<link name="link_3">
		<end_point_1 name="core_2">
			<port name="port1"/>
		</end_point_1>
		<end_point_2 name="localhost">
			<port name="port3"/>
		</end_point_2>
	</link>
	<link name="link_4">
		<end_point_1 name="core_3">
			<port name="port1"/>
		</end_point_1>
		<end_point_2 name="localhost">
			<port name="port4"/>
		</end_point_2>
	</link>
	<link name="link_5">
		<end_point_1 name="gpu">
			<port name="port1"/>
		</end_point_1>
		<end_point_2 name="localhost">
			<port name="port5"/>
		</end_point_2>
	</link>
</architecture>